1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
Recently, a packaging called wafer-level CSP is being developed, in which a wiring is formed on a semiconductor chip so as to form an external terminal (see JP-A-2003-282790). Provided under the wiring is a resin layer so that stress generated at the wiring is distributed and absorbed. However, when the surface (active surface), on which an integrated circuit is formed, is covered by the resin layer, heat release performance is deteriorated. Further, the wiring can hardly dissipate heat, because the wiring is covered by a solder mask except a land, on which a solder ball is to be laid. Accordingly, when the semiconductor device is mounted on a mother board, most of heat generated in the integrated circuit is disadvantageously transferred to the mother board intensively on the external terminal. Therefore, there arises an adverse effect due to heat on the mother board.